Behavioural modeling of an analog to digital converter

Abstract

The thesis applies behavioral modeling to create and simulate an 8-bit pipeline analog-to- digital converter (ADC) using Verilog-A in the Cadence design environment. Many high- speed, medium-resolution applications, such as communication systems, signal processing, and data acquisition, rely on pipeline ADCs where accuracy and performance are equally important. However, their performance is often limited by analog non-idealities such as comparator offset, operational amplifier (OPAMP) gain, incomplete settling, capacitor mismatch, and clock jitter; all of these can result in degraded linearity and precision. To address these challenges, this work develops a modular Verilog-A model of a pipeline ADC that supports simulation and early-stage architecture validation. Each pipeline stage is implemented with functional blocks including a sample-and-hold (S/H) unit, low-resolution sub-ADC, digital-to-analog converter (DAC), and multiplying DAC (MDAC). Advanced techniques like OTA sharing and double sampling are included in the design to reduce area and power usage. The model correctly simulates the behavior by integrating the important idealities. Key parameters of the circuit, such as comparator threshold, OPAMP gain, capacitor ratios, and clocking, are considered in an idealized form to validate the fundamental functionality. The simulation results ensure the accuracy of the model by illustrating the behavior of the residue, the output, and how the product breaks down under ideal conditions. This demonstrates that the use of Verilog-A simulation accelerates the verification of the system architecture and explains the reasons behind performance issues. It allows analog designers to establish precise expectations for the whole system and minimizes the use of detailed transistor simulations at the beginning of the process.