Latency/area efficient data compression accelerators for improved resource utilization in mmWave radar SoCs

Abstract

The rapid advancement of autonomous driving (AD) and advanced driver-assistance systems (ADAS) has driven extensive research and technological development in automotive radar systems. Among the various sensor technologies being used, frequency modulated continuous wave (FMCW) radars play an important role in ensuring reliable detection due to their robustness to harsh weather and lighting conditions. To achieve very high angular resolution, the number of transmit/receive (Tx/Rx) chains has increased significantly in multiple-input multiple-output (MIMO) radars. Moreover, the incorporation of imaging and cooperative radar features to enhance driving safety has also led to an increase in Tx/Rx data processing chains. However, this increase in Tx/Rx data processing chains also leads to a significant increase in data volume, creating critical challenges in real-time data transfer, storage, and processing within radar systems-on-chip (SoCs).

Real-time transfer bandwidth and on-chip memory are important but limited resources on SoCs. The work presented in this thesis addresses the growing need for efficient radar in-phase and quadrature (IQ) data compression to optimize transfer bandwidth utilization between digital front-end (DFE) and baseband processing units. Using real on-air radar data analysis from TI IWR1642 77 GHz radar SoC, we design, implement, and evaluate three real-time data compression techniques optimized for FMCW radar systems. Two lossy compression methods are based on block floating point (BFP) and block scaling compression (BSC) techniques. We also design a lossless compression method called interleaved high bytes (IHB) data compression.

We implement our approaches on a low-cost Field-Programmable Gate Array (FPGA). Our implementation design focuses on the minimization of processing latency and computational resources. Our results show that the two proposed lossy techniques can achieve 50% radar data compression without degrading the radar range and Doppler Fast Fourier Transform (FFT) performance. However, the BFP-based approach requires fewer logic resources and incurs minimum latency compared to the BSC-based method. The lossless compression method can compress up to 38% of radar data.

We evaluate the results and trade-offs of the different techniques, their feasibility in terms of FPGA resources, latency, and timing constraints. It is concluded that the BFPbased method offers the best performance in terms of processing latency, resource utilization, and reduced bandwidth utilization, while incurring minimal accuracy loss, which does not degrade radar detection performance. This study underscores the viability of lightweight compression methods to enhance scalability and optimize radar SoC performance for next-generation ADAS and AD applications, ensuring efficient data handling without compromising detection fidelity.