Continuous integration & release framework for system-on-chip verification

Abstract

System-on-Chip (SoC) development presents unique challenges for Continuous Integration and Continuous Delivery (CI/CD) due to the scale and complexity of hardware designs, where extensive compilation and simulation times and hardware resources are necessary to validate each change. Conventional CI/CD solutions are primarily focused on software projects and lack the specialized features needed for hardware design workflows. Typically, these solutions run automated build and test processes on feature branches and only merge into the main repository once the changes have passed all checks, ensuring code stability and reducing the risk of introducing errors. However, in hardware design, manual intervention is still needed for large-scale simulations, causing delays and risking codebase stability.

This thesis proposes a Continuous Integration and Release framework for Complex System-on-Chip Development, a semi-automated CI/CD pipeline designed to address these limitations. The proposed approach incorporates a batching and bisecting mechanism that groups commits from multiple developers, staging and validating each batch independently before merging any changes into the master repository. By testing grouped changes in isolated batches, it ensures efficient and resource-optimized simulation runs, with problematic contributions automatically isolated from stable changes. Furthermore, a focused divide-and-conquer bisection technique is applied while batching to identify the exact failures.

A key advantage of this approach is the stability it provides to the master codebase. By releasing only validated, stable code, the pipeline guarantees that every integration into the master branch maintains the health of the codebase, ensuring that each release is production-ready and of high quality. This automation not only reduces the manual workload for developers but also accelerates the development process by preventing unstable code from merging. This pipeline provides a scalable and resource-efficient solution tailored specifically for complex System-on-Chip projects, enabling reliable and continuous integration that enhances both development speed and product stability.