Modeling of ferroelectric field-effect transistors and their application in non-volatile SRAM
Haidar, Muhammad Zeeshan (2025-06-16)
Haidar, Muhammad Zeeshan
M. Z. Haidar
16.06.2025
© 2025 Muhammad Zeeshan Haidar. Ellei toisin mainita, uudelleenkäyttö on sallittu Creative Commons Attribution 4.0 International (CC-BY 4.0) -lisenssillä (https://creativecommons.org/licenses/by/4.0/). Uudelleenkäyttö on sallittua edellyttäen, että lähde mainitaan asianmukaisesti ja mahdolliset muutokset merkitään. Sellaisten osien käyttö tai jäljentäminen, jotka eivät ole tekijän tai tekijöiden omaisuutta, saattaa edellyttää lupaa suoraan asianomaisilta oikeudenhaltijoilta.
Julkaisun pysyvä osoite on
https://urn.fi/URN:NBN:fi:oulu-202506164534
https://urn.fi/URN:NBN:fi:oulu-202506164534
Tiivistelmä
Ferroelectric Field-Effect Transistors (FeFETs) are gaining attention as promising solutions for non-volatile memory applications due to their fast-switching speed, low power operation, and inherent capability for non-destructive readout. Despite recent advancements, accurate device-level modeling remains critical for evaluating their performance in circuit-level applications. This thesis was focused on the modeling and simulation of FeFETs in the Cadence Virtuoso environment. A standalone ferroelectric capacitor (FeCap) model was developed using the Landau–Khalatnikov equation to capture polarization switching dynamics. Although this FeCap model was not integrated into a FeFET structure, it was created to understand the standalone switching behavior prior to future integration. A previously validated FeFET model from existing literature was employed to simulate a hybrid Static Random Access Memory (SRAM) cell, combining n-type FeFET pull-down transistors with conventional PMOS devices. The study explored the effect of varying ferroelectric thickness on the bistability and retention characteristics of the SRAM. Through dynamic waveform simulations, a critical thickness threshold was identified, beyond which the FeFET exhibits stable non-volatile switching. This work provides insight into the importance of ferroelectric thickness for memory functionality and offers a simulation-based methodology for future FeFET-based circuit design.
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