Analysis and design of a power amplifier in 22-nm FDSOI technology for FR3 band transmitters

Abstract

The continuous evolution toward sixth-generation (6G) wireless communication systems demands high data rates, wide coverage and high efficiency. Meeting these strict requirements, significant advancements are required in the design of radio frequency (RF) front-end components, particularly power amplifiers (PAs) operating in the newly suggested FR3 frequency band (7–24 GHz). However, PA design at these frequencies presents distinct challenges related to achieving high output power, back-off efficiency, linearity, and managing high peak-to-average power ratios (PAPR).

This thesis investigates the design and optimization of various PA topologies using Global Foundries’ advanced 22 nm Fully Depleted Silicon-On Insulator (FD-SOI) technology. Building on this, multiple PA topologies were systematically designed and analyzed, including single-ended two stack and three-stack designs, as well as three-stack differential configurations employing transformer-based matching networks.

Performance evaluations revealed important trade-offs associated with transistor stacking, device sizing, impedance matching approaches, and parasitic effects. In particular, schematic level simulations of a three-stack differential PA with transformer-based matching demonstrated optimal performance, achieving \(P_{\rm{sat}}\) of approximately 23.5 dBm, power gain exceeding 30 dB , and peak power-added efficiency (PAE) above 36%. However, due to time constraints only initial PEX simulations were completed.

This thesis shows that 22 nm FD-SOI technology is a practical and effective option for FR3-band 6G power amplifiers, particularly when employing optimized differential stacked topologies. Although inherent limitations in CMOS technologies need advanced power-combining techniques to achieve output powers above 30 dBm, the investigated designs already exhibit promising performance benchmarks.