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Machine learning based design of broadband amplifiers

Batool, Sumra (2025-04-16)

 
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Batool, Sumra
S. Batool
16.04.2025
© 2025, Sumra Batool. Tämä Kohde on tekijänoikeuden ja/tai lähioikeuksien suojaama. Voit käyttää Kohdetta käyttöösi sovellettavan tekijänoikeutta ja lähioikeuksia koskevan lainsäädännön sallimilla tavoilla. Muunlaista käyttöä varten tarvitset oikeudenhaltijoiden luvan.
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Julkaisun pysyvä osoite on
https://urn.fi/URN:NBN:fi:oulu-202504162746
Tiivistelmä
With advancements in wireless communication technologies, the FR3 frequency range has become a promising contender for next-generation applications. Its enhanced 3D coverage, increased flexibility, and improved sensing capabilities make it a key area of research. The necessity of high-performance, low-noise amplifiers (LNAs) in this frequency range is an important aspect of efficient signal transmission and reception. This thesis primarily aims to design an LNA in the FR3 frequency range while maintaining optimal linearity, low power consumption, high gain, and minimal noise figure. This thesis presents a detailed analysis of FR1, FR2, and FR3. The key performance indicators (KPIs), such as gain, noise figure, linearity, stability, return loss, center frequency, bandwidth, and power consumption, are evaluated to ensure optimal performance. A criteria for machine learning-based optimization approach is explored based on figures of merit (FoMs) such as FoM\(_N\) (for noise), FoM\(_s\) (for sensitivity), FoM\(_D\) (dynamic range), and FoM\(_{BWD}\) (bandwidth-aware dynamic range). The performance of the LNA is analyzed across different frequencies, specifically at 7 GHz, 15 GHz, and 24 GHz in the FR3 frequency range based on the above FoMs. The design uses the cascaded common source topology with source degeneration through inductance. The step-by-step approach, including DC biasing, transistor sizing, and impedance matching, is used to improve noise matching and gain. Layout-level design and simulations are conducted to analyze the impact of parasitics. CMOS silicon-on-insulator (SOI) technology was used for the design.

The LNA is designed at 15 GHz, and has a noise figure of 1.7 dB, with a 3 dB bandwidth of 6.4 GHz. The gain observed is 14.5 dB. The 1 dB compression point is measured at -11.1 dBm, while the IIP3 is at 1.1 dBm. The LNA operates with a supply voltage of 1.3 V and has a power consumption of 7.6 mW. The figure of merits is calculated for the designed LNA. The observed results were found to be comparable to those of state-of-the-art LNAs. However, there is still room for improvements in terms of noise figure, linearity, and, particularly, bandwidth. The wideband matching techniques can help to broaden the bandwidth. Moreover, by using the discussed FOMs, machine learning techniques can automate the design process and further optimize the LNA’s performance.
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