Highly linear on-chip delay generator for a depth profiling CMOS SPAD Raman sensor
Amin, Belal Mostafa; Nissinen, Ilkka (2024-11-18)
IEEE
18.11.2024
B. M. Amin and I. Nissinen, "Highly linear on-chip delay generator for a depth profiling CMOS SPAD Raman sensor," 2024 IEEE Nordic Circuits and Systems Conference (NorCAS), Lund, Sweden, 2024, pp. 1-6, doi: 10.1109/NorCAS64408.2024.10752444.
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© 2024 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
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Julkaisun pysyvä osoite on
https://urn.fi/URN:NBN:fi:oulu-202504162699
https://urn.fi/URN:NBN:fi:oulu-202504162699
Tiivistelmä
Abstract
Raman Spectroscopy usage for depth profiling of samples is gaining a lot of interest. In this paper, we present a highly linear, high-resolution Time-Resolving CMOS SPAD Raman sensor. It employs an on-chip delay generator that allows the sensor to overcome challenging problems in comparison to previous generation of sensors, such as linearity, background rejection and measuring at specific depths only with up to 20 ps of resolution. The sensor architecture includes 128 spectral channels, an on-chip delay generation block, 1-bit TDC and 15-bit counter. The post-layout simulations showed that the non-linearity of the on chip delay generator based on a parallel-connected delay lines was decreased by the factor of 3.1 at the best compared to a basic delay line structure, and 20 ps delay stepping was achieved at every extreme process corner with temperature variation of −10∘C to +60∘C.
Raman Spectroscopy usage for depth profiling of samples is gaining a lot of interest. In this paper, we present a highly linear, high-resolution Time-Resolving CMOS SPAD Raman sensor. It employs an on-chip delay generator that allows the sensor to overcome challenging problems in comparison to previous generation of sensors, such as linearity, background rejection and measuring at specific depths only with up to 20 ps of resolution. The sensor architecture includes 128 spectral channels, an on-chip delay generation block, 1-bit TDC and 15-bit counter. The post-layout simulations showed that the non-linearity of the on chip delay generator based on a parallel-connected delay lines was decreased by the factor of 3.1 at the best compared to a basic delay line structure, and 20 ps delay stepping was achieved at every extreme process corner with temperature variation of −10∘C to +60∘C.
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