Improvements in UVM-based AXI verifcation IP for design verifcation

Abstract

The growing complexity of modern digital designs necessitates robust verification methodologies to ensure the correctness and reliability of integrated circuits (ICs). Among these methodologies, the Universal Verification Methodology (UVM) has emerged as a widely adopted framework for verification environments. In a UVM environment, verification IPs (Intellectual Properties) are essential for constructing reusable environments and tests which streamline the design verification process. Therefore, this thesis at Nokia focused on improving an in-house UVM-based Advanced eXtensible Interface (AXI) Verification IP (VIP). The AXI4 VIP is a Verification IP that adheres to UVM and was created to support the functionalities of the AXI protocol. AXI 4.0, an Advanced Microcontroller Bus Architecture (AMBA) family member, is a widely used interface protocol in System-on-Chip (SoC) designs, enabling high-speed communication among IC components. By leveraging UVM methodology, the thesis explores standardized approaches to functional verification and interoperability testing, including constrained-random testing, coverage-driven verification, and improving various aspects of the verification process, which is one of the factors needed to pave the way for faster time-to-market and improved product quality.