Exploration of methods and solutions for reset domain crossings in a complex SoC

Abstract

The thesis document titled ”Exploration of Methods and Solutions for Reset Domain Crossings in Complex SoC” presents a comprehensive study focused on addressing the challenges associated with reset domain crossings in complex SoC designs. Research underscores the critical nature of RDC issues, which, if not properly managed, can lead to system failures that are difficult to detect and correct in the later stages of design and validation. The thesis discusses the basic principles related to reset architectures in SoCs, emphasizing the importance of careful planning and execution of reset strategies to guarantee reliable system initialization and recovery procedures. The text explores the complexities of RDC, highlighting the risk of metastability and the significance of synchronization among various reset domains to maintain the integrity of the system.

A significant contribution of this thesis is the development of guidelines and automated verification processes aimed at early detection and resolution of RDC issues in both block-level designs and system-level integration. Using advanced statistic verification tools, a streamlined approach is proposed that integrates seamlessly with existing design and verification workflows.

The thesis also evaluates the effectiveness of the proposed solutions through practical application in an industrial design environment, demonstrating their potential to significantly improve the management of RDC in complex SoC projects. The results indicate a promising avenue for further research and development, with the potential for wide adoption in the semiconductor industry. In general, the document offers insight into the challenges and solutions associated with RDC in SoC design, providing a solid foundation of knowledge related to the field.