Improving regression reporting on SoC verification

Abstract

This thesis addresses the need for accurate and precise reporting of the results obtained from the regression testing in the verification phase of System on Chip (SoC) designs. The verification process aims to ensure the absence of functional errors in the hardware design. However, as hardware complexity increases, these techniques demand greater effort. With growing SoC design complexity, timely and accurate information about the design is process is essential.

This thesis evaluates the current reporting situation in SoC design and verification, analysing different metrics used as part of these reports. It identifies limitations in existing reporting practices, particularly the lack of detailed insights and timeline features. In response, a prototype reporting solution is developed to enhance the current reporting practices.

By processing the output reports of regression tests, this prototype provides a more comprehensive and effective reporting mechanism that can streamline the verification process by improving the information available for decision making. This prototype was tested using the results of 10 regressions and was proven to work effectively, validating the effectiveness of the design.