Järjestelmämikropiirin fyysisen suunnittelun huomioonottava tehon optimointi

Abstract

The purpose of this thesis was to investigate how physical components affect power estimation results and to see if taking them into account is viable. Physical Components include clock tree, multi-bit flip flops, placement of standard cells and routing post clock tree synthesis. This was done by comparing the power calculated at the post-synthesis stage (power estimated using gate-level netlist) and the post-layout stage in the Nokia ASIC design flow. The thesis consists of a theoretical framework part which is followed by the flow setup and analysis. In the theoretical part, the types of power consumption based on CMOS technology were followed by a brief overview of the different kinds of power estimation methods in SoCs. In addition, the ASIC design flow is explained in detail and the different stages in the flow where the power is estimated are discussed. For analysis, five IP blocks were taken to estimate the power numbers at the post-layout stage of the ASIC design flow by using different EDA tools. Different use cases were used for each of these IPs focusing on the different modes in which they function. Detailed power estimation was done for all use cases at the post-layout stage and the results were compared to the power estimated at the post-synthesis stage. For the power estimation, switching activity was used from the RTL simulations. Additionally, constraints, parasitics and netlists were used from the post-layout stage and conclusions were drawn based on the difference in power numbers at the two different stages of the design flow. Furthermore, analysis was done if taking the physical components into account is feasible.