A fast convergence unbiased low complexity method for digital pre-distorter parameter estimation : algorithm and architecture

Abstract

The continuously growing data rates demand increasing energy efficiency from radio access networks. The radio frequency (RF) power amplifier (PA) that is responsible for driving power to the transmit antenna usually consumes the most power in the system. Thus, it is imperative to enhance its efficiency. Digital pre-distortion (DPD) is a popular technique for enabling the RF-PA to operate near saturation, where it is most efficient. In that operating region, the RF-PA produces severe distortion due to non-linearity and the DPD aims to compensate for it. A typical DPD employs a Volterra-based model with complex coefficients as adaptable variables to facilitate good performance in different operating conditions. The coefficients are estimated based on a feedback signal from the RF-PA output. A speedy estimation process enables the radio to spend a longer time in power-saving modes. The accuracy of the estimation dictates how close to the saturation the RF-PA can be operated without generating too much distortion.

This thesis studies different learning architectures and linear system identification algorithms for adaptive digital pre-distortion. Commercial application-specific integrated circuit (ASIC) implementation is considered, making the computational complexity an important factor. After building the necessary background on the RF-PA non-idealities and Volterra-based non-linear models, the system identification algorithms are compared in terms of performance, and complexity. A new algorithm is proposed. The performances of different algorithms are simulated in a Volterra filter coefficient estimation. Different learning architectures are presented and analyzed. Their performance is compared with simulation with different RF-PA models in different operating points with 5G waveforms.

When the convergence speed, linearization performance, and complexity are considered, the dual loop learning architecture (DLLA) is found to be unparalleled when implemented with shared hardware (HW) resources as proposed in this thesis. Targeting extremely fast convergence speed, the DLLA with the QR decomposition-based recursive least squares (QRD-RLS) algorithm implemented as a HW accelerator is propounded. The proposal is backed up with the results of the extensive simulations. A novel architecture for the accelerator is designed, with shared resources for both loops in the DLLA, and a fixed-point MATLAB model for it is built. A unique solution is presented for the QRD-RLS coefficient extraction problem. With simulations, the architecture is validated with s24.12 number format, which is signed two’s complement binary point scaling format with 12 integer and 12 fractional bits, with some signals employing s13.12. Finally, the resource requirements for implementing the architecture in an ASIC are estimated.