Implementation of Ultra-Fast Polar Decoders
Rezaei, Hossein; Ranasinghe, Vismika; Rajatheva, Nandana; Latva-aho, Matti; Park, Giyoon; Park, Ok-Sun (2022-07-11)
IEEE
11.07.2022
H. Rezaei, V. Ranasinghe, N. Rajatheva, M. Latva-aho, G. Park and O. -S. Park, "Implementation of Ultra-Fast Polar Decoders," 2022 IEEE International Conference on Communications Workshops (ICC Workshops), Seoul, Korea, Republic of, 2022, pp. 235-241, doi: 10.1109/ICCWorkshops53468.2022.9814456.
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Julkaisun pysyvä osoite on
https://urn.fi/URN:NBN:fi:oulu-202401221366
https://urn.fi/URN:NBN:fi:oulu-202401221366
Tiivistelmä
Abstract
Polar codes are used in the 5G standard, and due to their low-complexity decoding algorithm and the ability to achieve symmetric channel capacity, they are receiving increased research interest for beyond 5G networks as well. In our recent work, we have introduced new subcodes and their decoding algorithms for fast decoding of polar codes with short to moderate blocklengths. In this paper, we study the algorithms from a hardware implementation point of view. Moreover, some new subcodes are also introduced to further prune the binary decoder tree. A hardware architecture of the algorithms using resource sharing and multiplexing techniques is presented. The FPGA implementation results show that a polar code of length N=102A , rate R=1/2 with two Processing Element (Pe) values of 128 and 256 achieves 42.5% and 47.6% lower latency comparing to the original Fast-SSC algorithm. The proposed decoder architecture offers an information throughput of 393 Mbps for the same code with Pe=128 .
Polar codes are used in the 5G standard, and due to their low-complexity decoding algorithm and the ability to achieve symmetric channel capacity, they are receiving increased research interest for beyond 5G networks as well. In our recent work, we have introduced new subcodes and their decoding algorithms for fast decoding of polar codes with short to moderate blocklengths. In this paper, we study the algorithms from a hardware implementation point of view. Moreover, some new subcodes are also introduced to further prune the binary decoder tree. A hardware architecture of the algorithms using resource sharing and multiplexing techniques is presented. The FPGA implementation results show that a polar code of length N=102A , rate R=1/2 with two Processing Element (Pe) values of 128 and 256 achieves 42.5% and 47.6% lower latency comparing to the original Fast-SSC algorithm. The proposed decoder architecture offers an information throughput of 393 Mbps for the same code with Pe=128 .
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