Inter-processor communication in virtualized environment

Abstract

Modern SoC projects are becoming increasingly more complex every year. Industry demands in power efficiency and performance have forced a change in architecture of SoCs to use less flexible, but more efficient ASICs instead of general-purpose FPGAs. On the other hand, requirements of flexibility, for example in telecommunication base band SoCs due to multi-mode operability (3G to 5G), has forced a change in architecture to use ASIPs. ASIPs achieve the generalization of hardware into instruction-set processor-based solutions while also achieving good performance and power efficiency. This change has increased the software complexity of the design and demand for left shift in design flow.

In this thesis, a proof-of-concept solution is proposed for high abstraction level model target simulation, which would allow an aggressive left shift in the design flow of heterogeneous multi-processor system-on-chips. Main technical challenge in the proof-of-concept implementation is the inter-processor communication between multiple different high abstraction level model target simulations.

The implemented proof-of-concept starts up three different processors, with three different operating systems, on three separate QEMUs and enables reads and writes to distributed shared memory through Target SoC Simulator. This is an easy to use and modify transaction-level model of a heterogeneous multi-processor system-on-chip.

The implemented proof-of-concept verifies that it is possible to create a high abstraction level model of a heterogeneous multi-processor system and the inter-processor communication between them by using the tools chosen in the implementation. In terms of validation, the model is correct in terms of facilitating in-order transactions between the CPUs, but it does not model timed transactions.