NTHPC: Embracing Near-Threshold Operation for High Performance Multi-core Systems
Chakraborty, Shounak; Safarpour, Mehdi; Silvén, Olli (2023-11-07)
Springer Publishing Company
07.11.2023
Chakraborty, S., Safarpour, M., Silvén, O. (2023). NTHPC: Embracing Near-Threshold Operation for High Performance Multi-core Systems. In: Silvano, C., Pilato, C., Reichenbach, M. (eds) Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2023. Lecture Notes in Computer Science, vol 14385. Springer, Cham. https://doi.org/10.1007/978-3-031-46077-7_3
https://rightsstatements.org/vocab/InC/1.0/
© 2023 The Author(s), under exclusive license to Springer Nature Switzerland AG. This version of the article has been accepted for publication, after peer review (when applicable) but is not the Version of Record and does not reflect post-acceptance improvements, or any corrections. The Version of Record is available online at: https://doi.org/10.1007/978-3-031-46077-7_3. Use of this Accepted Version is subject to the publisher’s Accepted Manuscript terms of use https://www.springernature.com/gp/open-research/policies/accepted-manuscript-terms”
https://rightsstatements.org/vocab/InC/1.0/
© 2023 The Author(s), under exclusive license to Springer Nature Switzerland AG. This version of the article has been accepted for publication, after peer review (when applicable) but is not the Version of Record and does not reflect post-acceptance improvements, or any corrections. The Version of Record is available online at: https://doi.org/10.1007/978-3-031-46077-7_3. Use of this Accepted Version is subject to the publisher’s Accepted Manuscript terms of use https://www.springernature.com/gp/open-research/policies/accepted-manuscript-terms”
https://rightsstatements.org/vocab/InC/1.0/
Julkaisun pysyvä osoite on
https://urn.fi/URN:NBN:fi:oulu-202311283397
https://urn.fi/URN:NBN:fi:oulu-202311283397
Tiivistelmä
Abstract
System-on-Chip (SoC) manufacturers use Core Level Redundancy (CLR) scheme to cope with fabrication defects. By providing redundancy with extra cores and logic blocks, CLR ensures delivering performance even if a small number of the functional units are defective. CLR even enables selling lower end products if more cores have failed than needed by the most demanding applications. In the current contribution the mechanisms built for CLR are used to increase throughput while complying with the Thermal Design Power (TDP) constraints. We propose NTHPC, that utilizes the designed redundancy support to improve system performance without violating thermal limits. This is done by operating the logic at a voltage close to the threshold voltage of the transistors. Our study using an Intel Xeon multiprocessor shows that Near Threshold Computing (NTC) with CLR mechanisms for thermal controls enabled up to 10.8% average throughput improvement in comparison to plain power gating.
System-on-Chip (SoC) manufacturers use Core Level Redundancy (CLR) scheme to cope with fabrication defects. By providing redundancy with extra cores and logic blocks, CLR ensures delivering performance even if a small number of the functional units are defective. CLR even enables selling lower end products if more cores have failed than needed by the most demanding applications. In the current contribution the mechanisms built for CLR are used to increase throughput while complying with the Thermal Design Power (TDP) constraints. We propose NTHPC, that utilizes the designed redundancy support to improve system performance without violating thermal limits. This is done by operating the logic at a voltage close to the threshold voltage of the transistors. Our study using an Intel Xeon multiprocessor shows that Near Threshold Computing (NTC) with CLR mechanisms for thermal controls enabled up to 10.8% average throughput improvement in comparison to plain power gating.
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