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A voltage controlled oscillator with inductive divider design and analysis at frequencies above 100 GHz

Shafiullah, Yasir; Akbar, Rehman; Hietanen, Mikko; Pärssinen, Aarno (2020-11-24)

 
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https://doi.org/10.1109/NorCAS51424.2020.9265130

Shafiullah, Yasir
Akbar, Rehman
Hietanen, Mikko
Pärssinen, Aarno
Institute of Electrical and Electronics Engineers
24.11.2020

Y. Shafiullah, R. Akbar, M. Hietanen and A. Pärssinen, "A Voltage Controlled Oscillator with Inductive Divider Design and Analysis at Frequencies Above 100 GHz," 2020 IEEE Nordic Circuits and Systems Conference (NorCAS), Oslo, Norway, 2020, pp. 1-5, doi: 10.1109/NorCAS51424.2020.9265130

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© 2020 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
https://rightsstatements.org/vocab/InC/1.0/
doi:https://doi.org/10.1109/NorCAS51424.2020.9265130
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Abstract

Millimeter wave oscillators are of particular interest towards future communications and sensing as frequency multiplication of local oscillator signal is resulting in degraded performance. At high frequencies, the quality (Q) factor of the LC tank is degraded. Thus, a higher transconductance (GM) size is required to compensate the losses, thereby consuming high power. Numerous techniques have been adopted to reduce the power consumption of a cross-coupled LC voltage controlled oscillator (VCO) and to improve the negative resistance (Rneg) associated to it. One of them utilizes inductors in the cross-coupled pair. In this paper, we examine the tradeoffs of this inductor to improve negative resistance above 100 GHz. For the analysis, the transistor model is being verified with the simplified small-signal equivalent model. Moreover, we have studied the inductor influence on the transition frequencies of the cross-coupled pair. The restrictions of this technique at high frequencies is investigated. To study the benefits of this technique, an oscillator core is designed and simulated using the 22nm FDSOI CMOS process. It exhibits a tuning range of 5.4% from 125.5 GHz to 132.5 GHz, and phase noise from -101.23 dBc/Hz to -102.0381 dBc/Hz at 10 MHz offset over the entire tuning range. The VCO consumes power of 17 mW. In simulations, an improvement in power consumption by 4.3 mW and phase noise by 1.5 dBc/Hz were achieved when compared to conventional LC Tank VCO.

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