Digital timing error calibration of time-interleaved ADC with low sample rate

Neitola, Marko (2020-11-24)
 
Avaa tiedosto
Lataukset: 

URL:
https://doi.org/10.1109/NorCAS51424.2020.9264991

Neitola, Marko
Institute of Electrical and Electronics Engineers
24.11.2020

M. Neitola, "Digital Timing Error Calibration of Time-Interleaved ADC with Low Sample Rate," 2020 IEEE Nordic Circuits and Systems Conference (NorCAS), Oslo, Norway, 2020, pp. 1-7, doi: 10.1109/NorCAS51424.2020.9264991

https://rightsstatements.org/vocab/InC/1.0/
© 2020 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
https://rightsstatements.org/vocab/InC/1.0/
doi:https://doi.org/10.1109/NorCAS51424.2020.9264991
Näytä kaikki kuvailutiedot
Julkaisun pysyvä osoite on
https://urn.fi/URN:NBN:fi-fe2020113097420
Tiivistelmä

Abstract

This work suggests a novel procedure of calibrating timing mismatch of time-interleaved Analog-to-Digital conversion. Here, the timing mismatch calibration and compensation are both performed digitally. The proposed method is simple and it is able to find timing errors below the Nyquist rate of the individual analog-to-digital converter. Moreover, the method can be easily modified for digital gain error calibration.

Kokoelmat