Analysis and implementation of sdf radix-2 fft processor using verilog hardware description language

Lai, Phuong H.; Hoang, Manh; Tran, Viet Q.; Nguyen, Tung V.; Truong, Thien V.; Nguyen, Phong H. (2020-08-31)
 
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https://doi.org/10.30534/ijatcse/2020/144942020

Lai, Phuong H.
Hoang, Manh
Tran, Viet Q.
Nguyen, Tung V.
Truong, Thien V.
Nguyen, Phong H.
The World Academy of Research in Science and Engineering
31.08.2020

H. Lai, P. (2020). Analysis and implementation of SDF Radix-2 FFT processor using VERILOG Hardware Description Language. International Journal of Advanced Trends in Computer Science and Engineering, 9(4), 5185–5189. https://doi.org/10.30534/ijatcse/2020/144942020

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© The Authors 2020.
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doi:https://doi.org/10.30534/ijatcse/2020/144942020
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https://urn.fi/URN:NBN:fi-fe2020112092225
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Abstract

This paper will study a novel system on chip (SoC) design for fast Fourier transform (FFT) module. We first explain the role and position of FFT module in a digital intelligent system. Then, the discrete Fourier transform (DFT) and decimation in frequency (DIF) Radix-2 butterfly FFT algorithm is explained in detail, mathematically. In addition, the analysis of a simple pipeline FFT processor and a single-path delay feedback pipeline FFT processor based on SDF Radix-2 algorithm are discussed. Finally, the implementation and verification of proposed FFT processor are performed VERILOG hardware description language (HDL).

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