A 28 GHz static CML frequency divider with back-gate tuning on 22-nm CMOS FD-SOI technology

Hietanen, Mikko; Aikio, Janne; Akbar, Rehman; Rahkonen, Timo; Pärssinen, Aarno (2019-01-23)
 
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https://doi.org/10.1109/SIRF.2019.8709088

Hietanen, Mikko
Aikio, Janne
Akbar, Rehman
Rahkonen, Timo
Pärssinen, Aarno
Institute of Electrical and Electronics Engineers
23.01.2019

M. Hietanen, J. Aikio, R. Akbar, T. Rahkonen and A. Pärssinen, "A 28 GHz Static CML Frequency Divider with Back-Gate Tuning on 22-nm CMOS FD-SOI Technology," 2019 IEEE 19th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), Orlando, FL, USA, 2019, pp. 1-3. doi: 10.1109/SIRF.2019.8709088

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doi:https://doi.org/10.1109/SIRF.2019.8709088
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https://urn.fi/URN:NBN:fi-fe2019121748477
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Abstract

A divide-by-2 frequency divider circuit was designed using 22-nm CMOS FD-SOI technology. The circuit utilizes back-gate biasing which provides almost 4GHz additional output center frequency tuning range over other mechanisms leading to 21.3 to 30GHz operation range with 0dBm input signal. This covers 5G bands from 24.25 to 27.5GHz with good margin. Divider dissipates 11mW from 0.86V supply and occupies 800μm² of area. Small area allows to place divider-by-2 block next to IQ mixers in a direct conversion or sliding IF transmitter or receiver.

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