Optimum number of transistors in stacked CMOS millimeter-wave power amplifiers

Montaseri, Mohammad Hassan; Aikio, Janne; Rahkonen, Timo; Pärssinen, Aarno (2018-05-04)
 
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https://doi.org/10.1109/ISCAS.2018.8351160

Montaseri, Mohammad Hassan
Aikio, Janne
Rahkonen, Timo
Pärssinen, Aarno
Institute of Electrical and Electronics Engineers
04.05.2018

M. H. Montaseri, J. Aikio, T. Rahkonen and A. Pärssinen, "Optimum Number of Transistors in Stacked CMOS Millimeter-Wave Power Amplifiers," 2018 IEEE International Symposium on Circuits and Systems (ISCAS), Florence, 2018, pp. 1-4. doi: 10.1109/ISCAS.2018.8351160

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doi:https://doi.org/10.1109/ISCAS.2018.8351160
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Abstract

This paper proposes how to define the optimum number of stacked transistors in a multi-stacked CMOS power amplifier (PA) topology, based on several physical as well as circuit design aspects. Starting with a systematic concept, the analysis then goes through the relevance of transistor transconductance, aspect ratio, parasitics, operating frequency, and the number of transistor stages in a pentagonal trade-off concept. While this is done based on theoretical circuit analysis, the results, then, are evaluated using simulations based on 45nm CMOS technology.

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