Estimating the impact of methodology on analog integrated circuit design time
Jalas, Panu; Rahkonen, Timo (2015-11-03)
Institute of Electrical and Electronics Engineers
03.11.2015
P. Jalas and T. Rahkonen, "Estimating the Impact of Methodology on Analog Integrated Circuit Design Time," in IEEE Design & Test, vol. 34, no. 1, pp. 35-46, Feb. 2017. doi: 10.1109/MDAT.2015.2497331
https://rightsstatements.org/vocab/InC/1.0/
© 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
https://rightsstatements.org/vocab/InC/1.0/
© 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
https://rightsstatements.org/vocab/InC/1.0/
Julkaisun pysyvä osoite on
https://urn.fi/URN:NBN:fi-fe2018113049589
https://urn.fi/URN:NBN:fi-fe2018113049589
Tiivistelmä
Abstract
The article discusses analog design practices and proposes a project management model for studying which analog design methodology will achieve the fastest time-to-market given the probability of design errors.
Kokoelmat
- Avoin saatavuus [29959]