CMOS technology scaling advantages in time domain signal processing

Jansson, Jussi-Pekka; Keränen, Pekka; Kostamovaara, Juha; Baschirotto, Andrea (2017-07-07)
 
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https://doi.org/10.1109/I2MTC.2017.7969659

Jansson, Jussi-Pekka
Keränen, Pekka
Kostamovaara, Juha
Baschirotto, Andrea
Institute of Electrical and Electronics Engineers
07.07.2017

J. Jansson, P. Keränen, J. Kostamovaara and A. Baschirotto, "CMOS technology scaling advantages in time domain signal processing," 2017 IEEE International Instrumentation and Measurement Technology Conference (I2MTC), Turin, 2017, pp. 1-5. doi: 10.1109/I2MTC.2017.7969659

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doi:https://doi.org/10.1109/I2MTC.2017.7969659
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https://urn.fi/URN:NBN:fi-fe2018121851276
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Abstract

This paper compares two CMOS technologies, the robust 350nm version and its modern 28nm successor, in terms of time-domain signal processing parameters. The evaluated parameters; propagation delay, delay variation due to process and mismatch fluctuations, sensitivity to noise and area and power usage are crucial especially in measurement devices relying on precise timings, high precision time-to-digital converters, for example. Post-layout simulations show that the modern scaled technology offers superior speed, efficient area usage and low power consumption but suffers from considerable delay mismatch. Therefore applications relying on precise time domain signal processing do not always benefit from technology scaling.

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