Design of analog predistorter

Abstract

In this thesis, two analog predistorter circuits are designed for linearizing the CMOS power amplifier in MIMO transceivers. The first circuit uses two parallel transistors as conventional derivative superposition, where derivatives of the transistor drain currents are biased to have opposite phases for 3rd-order distortion components. This results in the cancellation and thus providing a very linear 3rd-order response. The other design, using complementary derivative superposition topology, has p- and n-type transistors with a common drain self-biasing to achieve expansive power gain. This is used to improve the 1-dB compression point of the CMOS power amplifier.

Simulation results of conventional derivative superposition circuit show over 25 dB improvement in distortion level, while still providing a fair amount of power gain. Implementation with a CMOS power amplifier shows a 2.6 dB improvement in 1 dB compression point. With the circuit having expansive characteristics, adjustable gain-expansion behaviour is achieved. With the implemented digital bias control, expansion between 2.5 dB and 4 dB is achieved, with gain variation between -2.4 dB and 1 dB. With a CMOS power amplifier, 3.5 dB improvement in 1 dB compression point is achieved, allowing the power amplifier to be used with greater efficiency. Both circuits are implemented using 22nm CMOS SOI technology and submitted to fabrication.